Derivados del 8051


Temic (8051 Family)
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80C31
8051 based CMOS contoller with, 32 I/O lines, 3 Timers/Counters, 5 Interrupts/4 priorty levels ROM-less, 128 Bytes on-chip RAM
80C31X2
8051 based CMOS contoller with Double UART, 60 MHz High-Speed Architecture, 32 I/O lines, 3 Timers/Counters, 5 Interrupts/4 priorty levels ROM-less, 128 Bytes on-chip RAM
80C51
8051 based CMOS contoller with 32 I/O lines, 3 Timers/Counters, 5 Interrupts/4 priorty levels 4K ROM, 128 Bytes on-chip RAM
80C51I2
8051 based CMOS contoller with 12ch PWM, Enhanced I/O ports, Multimaster II2 contr. 32 I/O lines, 2 Timers/Counters, 6 Interrupts/2 priorty levels 8K ROM, 256 Bytes on-chip RAM
80C51RA2
8051 based CMOS contoller with PCA, Dual DPTR, WDT, 60 MHz High-Speed Architecture, X2 function, 32 I/O lines, 3 Timers/Counters, 7 Interrupts/4 priorty levels ROM-less, 256 Bytes on-chip RAM, additional 256 Bytes XRAM
80C51RD2
8051 based CMOS contoller with PCA, Dual DPTR, WDT, 60 MHz High-Speed Architecture, X2 function, 32 I/O lines, 3 Timers/Counters, 7 Interrupts/4 priorty levels ROM-less, 256 Bytes on-chip RAM, additional 768 Bytes XRAM
80C51U2
8051 based CMOS contoller with Dual DPTR, Double UART, 60 MHz High-Speed Architecture, 32 I/O lines, 3 Timers/Counters, 7 Interrupts/4 priorty levels 16K ROM, 256 Bytes on-chip RAM
80C52X2
8051 based CMOS contoller with Dual DPTR, 60 MHz High-Speed Architecture, 32 I/O lines, 3 Timers/Counters, 6 Interrupts/4 priorty levels 8K ROM, 256 Bytes on-chip RAM
80C54X2
8051 based CMOS contoller with Dual DPTR, 60 MHz High-Speed Architecture, 32 I/O lines, 3 Timers/Counters, 6 Interrupts/4 priorty levels 16K ROM, 256 Bytes on-chip RAM
80C58X2
8051 based CMOS contoller with Dual DPTR, 60 MHz High-Speed Architecture, 32 I/O lines, 3 Timers/Counters, 6 Interrupts/4 priorty levels 32K ROM, 256 Bytes on-chip RAM
83/87C51RB2
8051 based CMOS contoller with PCA, Dual DPTR, WDT, 60 MHz High-Speed Architecture, X2 function, 32 I/O lines, 3 Timers/Counters, 7 Interrupts/4 priorty levels 16K ROM, 256 Bytes on-chip RAM, additional 256 Bytes XRAM
83/87C51RC2
8051 based CMOS contoller with PCA, Dual DPTR, WDT, 60 MHz High-Speed Architecture, X2 function, 32 I/O lines, 3 Timers/Counters, 7 Interrupts/4 priorty levels 32K ROM, 256 Bytes on-chip RAM, additional 256 Bytes XRAM
83/87C51RD2
8051 based CMOS contoller with PCA, Dual DPTR, WDT, 60 MHz High-Speed Architecture, X2 function, 32/48 I/O lines, 3 Timers/Counters, 7 Interrupts/4 priorty levels 64K ROM, 256 Bytes on-chip RAM, additional 768 Bytes XRAM
83/87C51U2
8051 based CMOS contoller with Dual DPTR, Double UART, 60 MHz High-Speed Architecture, 32 I/O lines, 3 Timers/Counters, 7 Interrupts/4 priorty levels 16K ROM, 256 Bytes on-chip RAM
83/87C52X2
8051 based CMOS contoller with 60 MHz High-Speed Architecture, 32 I/O lines, 3 Timers/Counters, 7 Interrupts/4 priorty levels 16K ROM, 256 Bytes on-chip RAM
87C51
8051 based CMOS contoller with, 32 I/O lines, 2 Timers/Counters, 5 Interrupts/2 priorty levels 4K OTP ROM, 128 Bytes on-chip RAM
T83C5101
8051 based CMOS contoller with PCA, Dual DPTR, enhanced UART, 66 MHz High-Speed Architecture, X2 function, 16+2 I/O lines, 3 Timers/Counters, 6 Interrupts/4 priorty levels 16K ROM, 256 Bytes on-chip RAM, additional 256 Bytes XRAM
T87C5101
8051 based CMOS contoller with PCA, Dual DPTR, enhanced UART, 66 MHz High-Speed Architecture, X2 function, 16+2 I/O lines, 3 Timers/Counters, 6 Interrupts/4 priorty levels 16K EPROM (OTP), 256 Bytes on-chip RAM, additional 256 Bytes XRAM
T89C51CC01
8051 based CMOS contoller with PCA, Dual DPTR, WDT, 10 Bit ADC, Full CAN, 40 MHz High-Speed Architecture, X2 function, 32+2 I/O lines, 3 Timers/Counters, 14 Interrupts/4 priorty levels 32K FLASH, 2K EEPROM, 256 Bytes on-chip RAM, additional 1K XRAM
T89C51RD2
8051 based CMOS contoller with PCA, Dual DPTR, WDT 40 MHz High-Speed Architecture, X2 function, 32+2 I/O lines, 3 Timers/Counters, 7 Interrupts/4 priorty levels 64K FLASH, 2K EEPROM (Boot Flash) , 256 Bytes on-chip RAM, additional 1K XRAM
  

Derivados del 8051